// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_glb_s_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:23:44 Create file
// ******************************************************************************

#ifndef __STARS_GLB_S_REG_REG_OFFSET_FIELD_H__
#define __STARS_GLB_S_REG_REG_OFFSET_FIELD_H__

#define STARS_GLB_S_REG_BYPASS_RES_CONFLICT_ERR_LEN    1
#define STARS_GLB_S_REG_BYPASS_RES_CONFLICT_ERR_OFFSET 8
#define STARS_GLB_S_REG_POOL_SEC_LEN                   1
#define STARS_GLB_S_REG_POOL_SEC_OFFSET                0

#define STARS_GLB_S_REG_VFG_SEC_LEN    1
#define STARS_GLB_S_REG_VFG_SEC_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_0_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_0_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_1_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_1_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_2_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_2_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_3_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_3_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_4_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_4_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_5_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_5_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_6_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_6_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_7_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_7_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_8_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_8_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_9_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_9_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_10_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_10_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_11_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_11_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_12_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_12_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_13_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_13_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_14_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_14_OFFSET 0

#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_15_LEN    32
#define STARS_GLB_S_REG_STARS_SQ_SEC_EN_15_OFFSET 0

#define STARS_GLB_S_REG_CFG_ARCACHE_DVPP_DESC_LEN    4
#define STARS_GLB_S_REG_CFG_ARCACHE_DVPP_DESC_OFFSET 1
#define STARS_GLB_S_REG_CFG_ARSNOOP_DVPP_DESC_LEN    1
#define STARS_GLB_S_REG_CFG_ARSNOOP_DVPP_DESC_OFFSET 0

#define STARS_GLB_S_REG_ARNS_DVPP_DESC_LEN            1
#define STARS_GLB_S_REG_ARNS_DVPP_DESC_OFFSET         3
#define STARS_GLB_S_REG_NS_SQ_ARPROT_DVPP_DESC_LEN    3
#define STARS_GLB_S_REG_NS_SQ_ARPROT_DVPP_DESC_OFFSET 0

#define STARS_GLB_S_REG_S_SQ_ARPROT_DVPP_DESC_LEN    3
#define STARS_GLB_S_REG_S_SQ_ARPROT_DVPP_DESC_OFFSET 0

#define STARS_GLB_S_REG_STARS_SEC_EN_LEN    1
#define STARS_GLB_S_REG_STARS_SEC_EN_OFFSET 0

#define STARS_GLB_S_REG_JPEGD_NS_SQ_USE_SEC_POOL_LEN      1
#define STARS_GLB_S_REG_JPEGD_NS_SQ_USE_SEC_POOL_OFFSET   15
#define STARS_GLB_S_REG_JPEGE_NS_SQ_USE_SEC_POOL_LEN      1
#define STARS_GLB_S_REG_JPEGE_NS_SQ_USE_SEC_POOL_OFFSET   14
#define STARS_GLB_S_REG_VPC_NS_SQ_USE_SEC_POOL_LEN        1
#define STARS_GLB_S_REG_VPC_NS_SQ_USE_SEC_POOL_OFFSET     13
#define STARS_GLB_S_REG_CMO_NS_SQ_USE_SEC_POOL_LEN        1
#define STARS_GLB_S_REG_CMO_NS_SQ_USE_SEC_POOL_OFFSET     12
#define STARS_GLB_S_REG_SDMA_NS_SQ_USE_SEC_POOL_LEN       1
#define STARS_GLB_S_REG_SDMA_NS_SQ_USE_SEC_POOL_OFFSET    11
#define STARS_GLB_S_REG_ACPU_NS_SQ_USE_SEC_POOL_LEN       1
#define STARS_GLB_S_REG_ACPU_NS_SQ_USE_SEC_POOL_OFFSET    9
#define STARS_GLB_S_REG_PCIEDMA_NS_SQ_USE_SEC_POOL_LEN    1
#define STARS_GLB_S_REG_PCIEDMA_NS_SQ_USE_SEC_POOL_OFFSET 8
#define STARS_GLB_S_REG_FFTS_NS_SQ_USE_SEC_POOL_LEN       1
#define STARS_GLB_S_REG_FFTS_NS_SQ_USE_SEC_POOL_OFFSET    7









#define STARS_GLB_S_REG_NS_SQ_AWPROT_CQ_LEN    3
#define STARS_GLB_S_REG_NS_SQ_AWPROT_CQ_OFFSET 8
#define STARS_GLB_S_REG_NS_SQ_ARPROT_SQ_LEN    3
#define STARS_GLB_S_REG_NS_SQ_ARPROT_SQ_OFFSET 0





#define STARS_GLB_S_REG_S_SQ_AWPROT_CQ_LEN    3
#define STARS_GLB_S_REG_S_SQ_AWPROT_CQ_OFFSET 8
#define STARS_GLB_S_REG_S_SQ_ARPROT_SQ_LEN    3
#define STARS_GLB_S_REG_S_SQ_ARPROT_SQ_OFFSET 0

#define STARS_GLB_S_REG_S_SQ_AWPROT_WRITE_VALUE_LEN    1
#define STARS_GLB_S_REG_S_SQ_AWPROT_WRITE_VALUE_OFFSET 8

#define STARS_GLB_S_REG_AWNS_CQ_LEN    1
#define STARS_GLB_S_REG_AWNS_CQ_OFFSET 8
#define STARS_GLB_S_REG_ARNS_SQ_LEN    1
#define STARS_GLB_S_REG_ARNS_SQ_OFFSET 0

#define STARS_GLB_S_REG_NS_ARPROT_WR_VALUE_LEN    3
#define STARS_GLB_S_REG_NS_ARPROT_WR_VALUE_OFFSET 9
#define STARS_GLB_S_REG_S_ARPROT_WR_VALUE_LEN     3
#define STARS_GLB_S_REG_S_ARPROT_WR_VALUE_OFFSET  5
#define STARS_GLB_S_REG_AWNS_WR_VALUE_LEN         1
#define STARS_GLB_S_REG_AWNS_WR_VALUE_OFFSET      0





#define STARS_GLB_S_REG_CORE_ID_CHECK_EN_LEN    1
#define STARS_GLB_S_REG_CORE_ID_CHECK_EN_OFFSET 15
#define STARS_GLB_S_REG_STARS_CORE_ID_LEN       15
#define STARS_GLB_S_REG_STARS_CORE_ID_OFFSET    0

#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_SDMA_S_LEN             7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_SDMA_S_OFFSET          24
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_FFTS_AIV_ONLY_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_FFTS_AIV_ONLY_S_OFFSET 16
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_CONDS_S_LEN            7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_CONDS_S_OFFSET         8
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_FFTS_S_LEN             7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_FFTS_S_OFFSET          0

#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_CMO_S_LEN      7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_CMO_S_OFFSET   24
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_JPEGE_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_JPEGE_S_OFFSET 16
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_JPEGD_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_JPEGD_S_OFFSET 8
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_VPC_S_LEN      7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_VPC_S_OFFSET   0

#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_FFTS_AIC_ONLY_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_FFTS_AIC_ONLY_S_OFFSET 24
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_MBLK_CPU_S_LEN         7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_MBLK_CPU_S_OFFSET      16
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_SBLK_CPU_S_LEN         7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_SBLK_CPU_S_OFFSET      8
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_PCIEDMA_S_LEN          7
#define STARS_GLB_S_REG_ACSQ_STRICT_MAX_PCIEDMA_S_OFFSET       0

#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_SDMA_S_LEN             7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_SDMA_S_OFFSET          24
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_FFTS_AIV_ONLY_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_FFTS_AIV_ONLY_S_OFFSET 16
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_CONDS_S_LEN            7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_CONDS_S_OFFSET         8
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_FFTS_S_LEN             7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_FFTS_S_OFFSET          0

#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_CMO_S_LEN      7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_CMO_S_OFFSET   24
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_JPEGE_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_JPEGE_S_OFFSET 16
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_JPEGD_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_JPEGD_S_OFFSET 8
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_VPC_S_LEN      7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_VPC_S_OFFSET   0

#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_FFTS_AIC_ONLY_S_LEN    7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_FFTS_AIC_ONLY_S_OFFSET 24
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_MBLK_CPU_S_LEN         7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_MBLK_CPU_S_OFFSET      16
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_SBLK_CPU_S_LEN         7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_SBLK_CPU_S_OFFSET      8
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_PCIEDMA_S_LEN          7
#define STARS_GLB_S_REG_ACSQ_RELAX_MAX_PCIEDMA_S_OFFSET       0

#define STARS_GLB_S_REG_WR_VALUE_RD_SOFT_AUTHORITY_LEN    1
#define STARS_GLB_S_REG_WR_VALUE_RD_SOFT_AUTHORITY_OFFSET 12
#define STARS_GLB_S_REG_WR_VALUE_RD_SOFT_VA_LEN           1
#define STARS_GLB_S_REG_WR_VALUE_RD_SOFT_VA_OFFSET        8
#define STARS_GLB_S_REG_WR_VALUE_WR_SOFT_VA_LEN           1
#define STARS_GLB_S_REG_WR_VALUE_WR_SOFT_VA_OFFSET        4
#define STARS_GLB_S_REG_WR_VALUE_WR_SOFT_AUTHORITY_LEN    1
#define STARS_GLB_S_REG_WR_VALUE_WR_SOFT_AUTHORITY_OFFSET 0

#define STARS_GLB_S_REG_RD_DVPP_BLKDIM_SOFT_VA_LEN              1
#define STARS_GLB_S_REG_RD_DVPP_BLKDIM_SOFT_VA_OFFSET           1
#define STARS_GLB_S_REG_RD_DVPP_BLKDIM_SOFT_VA_AUTHORITY_LEN    1
#define STARS_GLB_S_REG_RD_DVPP_BLKDIM_SOFT_VA_AUTHORITY_OFFSET 0

#endif // __STARS_GLB_S_REG_REG_OFFSET_FIELD_H__
